AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

ID 683465
Date 4/15/2021
Public
Document Table of Contents

B. HDMI TX Interface Register Map

The HDMI TX interface component presents two Avalon memory-mapped agent interfaces for connection to the Nios II processor.

The i2c_slave interface provides a mechanism to connect to the i2c Avalon memory-mapped agent interface on the HDMI protocol IP, which sits outside the Platform Designer system. The register map for this interface is in the HDMI IP User Guide

The info_slave interface primarily allows the Nios II to write the HDMI TX AVI Infoframe data from the HDMI TX IP. It also provides access to some signals associated to configuring the transceivers and PLLs that otherwise you need to access via PIOs.
Table 7.  HDMI TX Register Map

Address

(byte)

Address (Word) Permission Name Description
0 0 Writeable HDMI TX GCP HDMI General Control Packet for the HDMI TX IP
1 – 13 4 – 52 Writeable HDMI TX AVI Infoframe HDMI AVI Infoframe for the HDMI TX IP. The AVI Infoframe is input to the HDMI TX as a 112 bit signal. Bits[7:0] are the checksum and are automatically generated inside this component so are not exposed through the register map. Registers 1 through 13 each provide access to one byte of the remaining 104 bits of this interface, with bits[15:8] in register 1 and bits [103:96] in register 13
14 56 Writeable HDMI 2 Mode Bit[0] of this register indicates to the HDMI TX IP to transmit using HDMI 2.0 data rates
15 60 Writeable Unused Unused
16 64 Read only Status
  • Bit[0] indicates if a TX hot-plug has occurred
  • Bit[1] indicates if the transceiver calibration is busy.
  • Bit[2] indicates if the transceiver reconfig is busy
  • Bit[3] indicates if the PLL reconfig is busy
  • Bit[4] indicates if the IOPLL reconfig is busy
17 68 Writeable TX Hot-plug acknowledge Bit[0] of this register drives the TX hot-plug acknowledge signal
18 72 Writeable TX transceiver reset The value in bit[0] is driven onto the transceiver reset for the HDMI TX
19 76 Writeable TX PLL reset The value in bit[0] is driven onto the PLL reset for the HDMI TX
20 80 Writeable TX transceiver reconfig enable Writing 1 to bit[0] of this register enables reconfiguration of the TX transceiver settings
21 84 Writeable TX transceiver reconfig channel Sets which TX transceiver channel new settings should be applied to

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