Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Document Table of Contents

2.2.2. Partial Reconfiguration Design

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. You can define multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems with various functions that time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.

The Quartus® Prime Pro Edition software supports the PR feature for the Agilex™ 5, Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX device families.

PR provides the following advantages over a flat design:

  • Allows run-time design reconfiguration.
  • Increases scalability of the design through time-multiplexing.
  • Lowers cost and power consumption through efficient use of board space.
  • Supports dynamic time-multiplexing functions in the design.
  • Improves initial programming time through smaller bitstreams.
  • Reduces system downtime through line upgrades.
  • Enables easy system updates by allowing remote hardware change.
  • Supports a simplified compilation flow for partial reconfiguration.

For more information about the PR design, refer to the Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.