Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Document Table of Contents Converting Symbolic BDF Files to Acceptable File Formats

Starting from the Quartus® Prime Pro Edition software version 23.3, the compiler cannot synthesize schematic Block Design File (.bdf). You must convert it to an acceptable format, such as Verilog HDL or VHDL using the Intel Quartus Prime Standard Edition command quartus_map as shown in the following:

  • To convert your .bdf file to Verilog Design File (.v):
    quartus_map <project_name> --convert_bdf_to_verilog=<bdf_file_name>
  • To convert your .bdf file to VHDL Design File (.vhd):
    quartus_map <project_name> --convert_bdf_to_vhdl=<bdf_file_name>