Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Document Table of Contents

2.1. Design Planning

Design planning is an essential step in advanced FPGA design. System architects must consider the target device characteristics in order to plan for interface I/O, integration of IP, on-chip debugging tools, and use of other EDA tools.
Designers must consider device power consumption and programming methods when planning the layout. You can solve potential problems early in the design cycle by following the design planning considerations in this chapter.

By default, the Quartus® Prime software optimizes designs for the best overall results. However, you can adjust settings to better optimize one aspect of your design, such as performance, routability, area, or power utilization. Consider your own design priorities and trade-offs when reviewing the techniques in this chapter. For example, certain device features, density, and performance requirements can increase system cost. Signal integrity and board issues can impact I/O pin locations. Power, timing performance, and area utilization all affect one another. Compilation time is affected when optimizing these priorities.

Determining your design priorities early on helps you to choose the best device, tools, features, and methodologies for your design.

Table 6.  Checklist for Design Planning
Item Considerations Links
Create a design specification and test plan
  • Create detailed design specifications that define the system.
  • Specify the I/O interfaces for the FPGA.
  • Identify the different clock domains.
  • Include a block diagram of basic design functions.
  • Create a test plan for verification and ease of manufacture.
  • Consider a common design directory structure or source control system to make design integration easy.
  • Consider whether you want to standardize on an interface protocol for each design block.
Planning for Target Device or Board
  • Refer to the Product Selector tool to compare the specifications and features of Intel® FPGA devices and development kits.
  • Refer to the device family documentation for detailed device characteristics. View a summary of each device's resources by selecting a device in the Device dialog box (Assignments > Device).
  • Consider whether the device family meets your design requirements for high-speed transceivers, global or regional clock networks, and the number of phase-locked loops (PLLs).
  • Consider the density requirements of your design.
    • Devices with more logic resources and higher I/O counts can implement larger and more complex designs, but at a higher cost.
    • Smaller devices use lower static power.
    • Select a device larger than what your design requires if you may want to add more logic later in the design cycle, or to reserve logic and memory for on-chip debugging.
  • Consider requirements for types of dedicated logic blocks, such as memory blocks of different sizes, or digital signal processing (DSP) blocks to implement certain arithmetic functions.
  • Alternatively, create a system that targets a specific development board to accelerate the process of appropriately configuring, connecting, and validating IP for the target board.
Planning for Device Migration
  • Determine whether you want to migrate your design to another device density to allow flexibility when your design nears completion.
  • Target a small (less expensive) device and move to a larger device if necessary to meet your design requirements.
  • Develop a prototype of your design in a larger device to reduce optimization time and achieve timing closure more quickly, and then migrate to a smaller device after prototyping.
Note: Selecting a migration device impacts pin placement because some pins may serve different functions in different device densities or package sizes.
Planning for Intellectual Property (IP) Cores

Plan which I/O interfaces or blocks in the system you want to implement using IP cores.

Integrate functions into your design using Intel FPGA IP cores, many of which are available for production use in the Quartus® Prime software without additional license.

For IP cores that require additional licenses for production, use the Intel® FPGA IP Evaluation Mode, which allows you to program the FPGA to verify the IP in the hardware before you purchase the IP license.

Planning for Standard Interfaces
  • Use standard interfaces in system design to ensure compatibility between design blocks from different design teams or vendors.
  • Use the Quartus® Prime Interface Planner to accurately plan constraints for design implementation, prototype interface implementations, and rapidly define a legal device floorplan.
  • Use the Quartus® Prime Platform Designer system integration tool to use standard interfaces and speed-up system-level integration.
Quartus® Prime Pro Edition User Guide: Platform Designer
Planning for Device Power Consumption

Estimating power consumption early in the design cycle allows you to plan power budgets and avoid unexpected results when designing the PCB.

  • Use the Early Power Estimator (EPE) spreadsheet for older devices, such as the Arria® 10 and Cyclone® 10 families or to estimate power consumption before compiling or creating any source code.
  • Use the Quartus® Prime Power Analyzer to ensure that your design satisfies thermal and power supply requirements.
  • Use the Intel® FPGA Power and Thermal Calculator (PTC) to estimate power utilization for your design for Stratix® 10, Agilex™ 7, and Agilex™ 5 device families. PTC does not support older devices.
Planning for I/O Interfaces
  • Create a preliminary pin-out for an Intel FPGA with the Quartus® Prime Pin Planner before you develop the source code, based on standard I/O interfaces (such as memory and bus interfaces) and any other I/O requirements for your system.
  • Configure how to connect the functions and cores to each other by specifying matching node names for selected ports.
  • Create other I/O-related assignments for these interfaces or other design I/O pins in the Pin Planner.
  • Compile your design to automatically run I/O Assignment Analysis in Fitter to validate I/O-related assignments that you created or modified throughout the design process.
Planning for Other EDA Tools
  • Use supported standard third-party EDA synthesis tools to synthesize your Verilog HDL or VHDL design, and compile the resulting output netlist file in the Quartus® Prime software.
  • Use the simulator version that your Quartus® Prime software version supports for best results. You must also use the model libraries provided with your Quartus® Prime software version. Libraries can change between versions, which might cause a mismatch with your simulation netlist.
Planning for On-Chip Debugging Tools
  • Consider whether to include on-chip debugging tools early in the design process. Adding the debugging tools late in the design process can be more time-consuming and error-prone.
  • Consider the following debugging requirements when planning your design to support debugging tools:
    • JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.
    • Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic.
    • Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging.
    • Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which requires I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required. Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation.
    • Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core.
    • Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the tapped node names do not change during synthesis.
Planning HDL Coding Styles
  • Use synchronous design practices to consistently meet your design goals. In a synchronous design, a clock signal triggers all events. When you meet all register timing requirements, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.
    Note: Problems with asynchronous design techniques include reliance on propagation delays in a device, incomplete timing analysis, and possible glitches.
  • Use dedicated clock pins and clock routing for best results, and if you have PLLs in your target device, use the PLLs for clock inversion, multiplication, and division.
  • For clock multiplexing and gating, use the dedicated clock control block or PLL clock switchover feature instead of combinational logic, if these features are available in your device. If you must use internally generated clock signals, register the output of any combinational logic used as a clock signal to reduce glitches.
  • Consider the architecture of the device you choose so that you can use specific features in your design. For example, the control signals should use the dedicated control signals in the device architecture. Sometimes, you might need to limit the number of different control signals used in your design to achieve the best results.
  • HDL coding styles can have a significant effect on the quality of results for programmable logic designs. Follow the coding guidelines for inferring Intel FPGA IP and targeting dedicated device hardware, such as memory and DSP blocks.
  • Ensure that your design accounts for synchronization between any asynchronous clock domains. Consider using a synchronizer chain of more than two registers for high-frequency clocks and frequently-toggling data signals to reduce the chance of a metastability failure.
  • Use the Quartus® Prime software to analyze the average mean time between failures (MTBF) due to metastability when a design synchronizes asynchronous signals, and optimize your design to improve the metastability MTBF.
Planning your Project Path Length

Design files with lengthy file paths might cause an internal error in the Windows* version of the Quartus® Prime Pro Edition software. Windows has a 260-character maximum path length limitation on the combined length of a file name and its file path.

To reduce the length of a file path to a design file, Intel® strongly recommends creating, storing, or moving your Quartus® Prime project to a shorter path. For example:


Tip: There are several third-party software freely available to help you fix the long path issue for Windows.
Maximum Path Length Limitation
Table 7.  Factors to Consider When Using Debugging Tools During Design Planning Stages
Design Planning Factor Signal Tap

Logic Analyzer

System Console In-System Memory

Content Editor

Logic Analyzer Interface (LAI) Signal Probe In-System Sources

and Probes

Virtual JTAG IP Core
JTAG connections Yes Yes Yes Yes Yes Yes
Additional logic resources Yes Yes
Reserve device memory Yes Yes
Reserve I/O pins Yes Yes
Instantiate IP core in your HDL code Yes Yes