Intel® FPGA IP Portfolio

Accelerate. Optimize. Differentiate.

Whether you need help to expedite your design schedules, gain that extra performance to differentiate your products, or both, Intel can provide the solutions you need to be successful.

Maximize Performance and Productivity with Intel and Partner IP Portfolio

The Intel® FPGA Intellectual Property (IP) portfolio includes a unique combination of soft and hardened IP cores along with reference designs to complement your application’s performance and IP strategies. On top of that, our straightforward selection of development kits give you the flexibility to test multiple types of platforms using a single board.

Intel also simplified the IP evaluation process with a no-hassle licensing Intel® FPGA IP Evaluation Mode feature. In addition, Intel provides dynamically generated design examples that use your custom IP configuration and create an out-of-the-box hardware test platform to enable functionality and performance verification on hardware. All of these are available at your fingertips by simply downloading the Intel® Quartus® Prime Design Software.

What’s New in Intel® Quartus® Prime Design Software v21.1

PCI Express

  • MCDMA IP on P-tile with SR-IOV features (Intel® Stratix® 10 DX FPGA / Intel® Agilex™ FPGA).
  • R-tile Avalon Streaming IP enablement.
  • Various Root-Port / End Point / Transaction Layer-Bypass configurations.
  • R-tile PIPE (Phy interface for PCI Express) mode.
  • F-tile Avalon Streaming IP enablement.
  • Various Root-Port / End Point / Transaction Layer-Bypass configurations.
  • Special license (INI) is required for all R/F-tile IP enablement; User-guide is posted on the Intel® Agilex™ FPGA and SoC technical library.


  • Enablement on F-tile: Two configurations: 8 x 12.5 Gbps (NRZ); 6 x 53 Gbps (PAM4).


  • Support JESD204C and JESD204C.1 in both simulations and compliance tests.
  • Added 2-port device return loss model support.


  • F-tile: Improved support for General-Purpose Transceiver (FGT) and High-Speed Transceiver (FHT) which include new GUI and latest device model support.
  • Performance improvement with Intel Math Kernel Library (MKL) and multi-core CPU support.


  • Intel® Agilex™ FPGA E-Tile SCTH (Simulation, Timing-closure, Compile, H/w validation) support for the data rates: 2.4576G, 4.9152 G, 9.8304G, 10.1376G, 24.33024G.
  • Intel® Agilex™ FPGA F-Tile SCT (Simulation, Timing-closure, Compile, H/w validation) support for 4.9152G, 10.1376G, 12.1651G, and 24.3302G.


  • Intel® Agilex™ FPGA E-tile & F-tile SCT v3.0 support.


  • Comprehensive F-tile Ethernet IP enablement.