Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Document Table of Contents

2.2.1. Flat Design Vs. Incremental Block-based Design

With the Quartus® Prime Pro Edition software, you can either develop a flat design or a block-based design:
  • Flat Designs: In a flat compilation flow, the design hierarchy is flattened without design partitions and the Quartus® Prime software compiles the entire design in a “flat” netlist. Although the source code may be hierarchical, the compiler flattens and synthesizes all the design logic. Whenever you recompile the project, the compiler re-performs all available logic and placement optimizations on the entire design.

    The flat compilation flow does not require any planning for design partitions. However, because the Quartus® Prime software recompiles the entire design whenever you change your design, flat design practices may require more overall compilation time for large designs. Additionally, you may find that the results for one part of the design change when you change a different part of your design.

    If you plan to develop a small design with no plans to reuse or preserve blocks, use a flat design. However, flat designs are generally more difficult to optimize and debug because you cannot always isolate the timing issue.

  • Block-based designs: In block-based (hierarchical) flows, you can divide your design by creating design partitions. Block-based design flow is also known as modular or hierarchical design flow. You can designate a design block as a design partition to preserve or reuse the block. A design partition is a logical, named, hierarchical boundary assignment that you can apply to a design instance. Hierarchical flows allow you to isolate, optimize, and preserve compilation results for specific design blocks but require more design planning to ensure effective results.

    Using a hierarchical design methodology offers several advantages, such as:

    • Reuse design blocks with the same periphery configuration, share a synthesized design block with another designer, or replicate placed and routed IP in another project.
    • Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device.
    • Perform easier debugging and optimization of individual design blocks.
    • Assign the design hierarchy elements into logical partitions that are functionally independent.
    • Perform stand-alone block verification.
    • Use design blocks for reuse and preserve synthesis and timing results for blocks that are fully coded and meeting timing.
    • Preserve earlier results for a block you do not want to change when you change RTL code or compiler settings for another block in the design. The compiler produces different compilation results compared to previous settings and can cause timing violations in blocks that do not reflect the same corresponding code or setting changes. Block-based incremental compilation flow allows for preserving the block.
    • Partition a design, compile the design partitions separately, and reuse the results for unchanged partitions. You can preserve the performance of unchanged blocks and reduce the number of design iterations. The performance preservation of incremental block-based compilation allows you to focus timing closure on unpreserved partitions or on blocks that have difficulty meeting timing requirements

For more information about the block-based designing, refer to the Quartus® Prime Pro Edition User Guide: Block-Based Design.