Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/01/2024
Document Table of Contents Verifying Verilog Compilation Unit

Quartus® Prime Pro Edition synthesis uses a different method to define the compilation unit. The Verilog LRM defines the concept of compilation unit as “a collection of one or more Verilog source files compiled together” forming the compilation-unit scope. Items visible only in the compilation-unit scope include macros, global declarations, and default net types. The contents of included files become part of the compilation unit of the parent file. Modules, primitives, programs, interfaces, and packages are visible in all compilation units. Ensure that your RTL accommodates these changes.
Table 13.  Verilog Compilation Unit Differences
Other Quartus Software Products Quartus® Prime Pro Edition
Synthesis in other Quartus software products follows the Multi-file compilation unit (MFCU) method to select compilation unit files. In MFCU, all files compile in the same compilation unit. Global definitions and directives are visible in all files. However, the default net type is reset at the start of each file. Quartus® Prime Pro Edition synthesis follows the Single-file compilation unit (SFCU) method to select compilation unit files. In SFCU, each file is a compilation unit, file order is irrelevant, and the macro is only defined until the end of the file.
Note: You can optionally change the MFCU mode using the following assignment: set_global_assignment -name VERILOG_CU_MODE MFCU