1.3.2. Transceiver Transport Layer
To verify the data integrity of the payload data stream through the TX JESD204B IP core and transport layer,the DAC’s JESD core is configured to check short transport layer test pattern that is transmitted from FPGA’s test pattern generator. The DAC JESD core checks the transport layer test patterns based on F = 1, 2, 4 or 8 configuration. The short test pattern has a duration of one frame period and is repeated continu- ously for the duration of the test.
To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sinewave. Connect an oscilloscope to observe the waveform at the DAC analog channels.
This figure shows the conceptual test setup for data integrity checking.
|Test Case||Objective||Description||Passing Criteria|
|TL.1||Check the transport layer mapping using STPL test pattern.||
The following signals in altera_jesd204_transport_tx_top.sv are tapped:
The following signals in jesd204b_ed.sv are tapped:
The txframe_clk is used as the SignalTap II sampling clock.
Check the following status in the DAC:
|TL.2||Verify the data transfer from digital to analog domain||Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.||
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