AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

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ID 683452
Date 12/06/2016
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core and AD9162 Hardware Checkout Report
1. JESD204B IP Core and AD9162 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transceiver Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B IP Core and AD9162 Hardware Checkout Report

1.4. JESD204B IP Core and DAC Configurations

TheJESD204B IP Core parameters (L, M and F) in this hardware checkout are natively supported by the AD9162 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9162 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 6.  Parameter ConfigurationGlobal setting for all configuration:
  • N = 16
  • N' = 16
  • CS = 0
  • CF = 0
  • Subclass = 1
  • Lane Rate (Gbps) = 12.5
  • FPGA Device Clock (MHz) = 312.5 2
  • FPGA Management Clock (MHz) = 100
  • FPGA Frame Clock (MHz) = 312.53
  • FPGA Link Clock (MHz) = 312.54
  • Character Replacement = Enabled
  • PCS Option = Soft PCS
LMF HD S DAC Sampling Clock (GHz) DAC Interpolation Data Pattern5
124 0 1 5 16
  1. Sine
  2. Single pulse
  3. Constant
    • M0S0:0xF1E2
    • M1S0:0xD3C4
222 0 1 5 8
  1. Sine
  2. Single pulse
  3. Constant
    • M0S0:0xF1E2
    • M1S0:0xD3C4
324 0 3 3.75 4
  1. Sine
  2. Single pulse
421 1 1 5 4
  1. Sine
  2. Single pulse
  3. Constant
    • M0S0:0xF1E2
    • M1S0:0xD3C4
622 0 3 3.75 2
  1. Sine
  2. Single pulse
811 1 4 5 1
  1. Sine
  2. Single pulse
  3. Constant
    • M0S0:0xF1E2
    • M0S1:0xD3C4
    • M0S2:0xB5A6
    • M0S3:0x9780
821 1 2 5 2
  1. Sine
  2. Single pulse
  3. Constant
    • M0S0:0xF1E2
    • M0S1:0xD3C4
    • M1S0:0xB5A6
    • M1S1:0x9780
2 The device clock is used to clock the transceiver and IO PLL.
3 The frame clock is derived from the device clock using an IO PLL.
4 The link clock is derived from the device clock using an IO PLL.
5 Sine wave pattern is used in TL.2 and SCR.2 test cases to verify that pattern generated in the FPGA transport layer is transmitted by DAC analog channel. Single pulse pattern is used in deterministic latency measurement test cases DL.1 and DL.2 only. Constant pattern is used to check the STPL test. DAC does not support STPL test for modes with 3 and 6 lanes.
Level Two Title