AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

ID 683452
Date 12/06/2016
Public

1.3.3. Scrambling

With descrambler enabled, the transport layer test pattern checker at the DAC JESD core checks the data integrity of scrambler in the FPGA.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 4.  Scrambler Test Cases
Test Case Objective Description Passing Criteria
SCR.1 Check the functionality of the scrambler using short transport layer test pattern as specified in the parameter configuration.

Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core.

The signals that are tapped in this test case are similar to test case TL.1

Check the following status in the DAC:

  • STPL test status
  • Thejesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The STPL error for all DACs is checked in DAC register 0x32F and jesd204_tx_int signal should be deasserted.
SCR.2 Verify the data transfer from digital to analog domain

Enable descrambler at the DAC JESD core and scrambler at the TX JESD204B IP core.

Enable sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.

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