AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

ID 683452
Date 12/06/2016
Public

1.3.4. Deterministic Latency (Subclass 1)

Figure below shows a block diagram of the deterministic latency test setup. The AD9508 clock fan-out buffer provides periodic SYSREF pulses for both the AD9162 and JESD204B IP Core. The period of SYSREF pulses is configured to 2 Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 4. Deterministic Latency Test Setup Block Diagram

The FPGA generates a 16-bit digital sample with a value of 8000 hexadecimal number at the transport layer. The most significant bit of this digital sample has a logic 1 and this bit is pin out at FPGA. This bit is probed at oscilloscope channel 1. The DAC analog channel is probed at oscilloscope channel 2. With two's complement value of 8000h, a pulse with the amplitude of negative full range is expected at DAC analog channel output. The time difference between the pulses at channel 1 (t0) and channel 2 (t1) is measured. This is the total latency of the JESD204B link, the DAC digital blocks, and analog channel.

Table 5.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1 Measure the total latency. Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2. The latency should be consistent.
DL.2 Re-measure the total latency after DAC power cycle and FPGA reconfiguration. Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2. The latency should be consistent.

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