1.6. Test Result Comments
In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and until user data phase. The behavior of the TX JESD204B IP core meets the passing criteria.
No data integrity issue is observed from the short transport layer (STPL) test pattern checkers at DAC JESD core for all modes except with 3 and 6 lanes. In these modes, the DAC does not support the STPL test. Sine wave at transmitted frequency is observed at analog channel when sine wave generators in FPGA are enabled for all supported JESD modes.
In the deterministic latency measurement, consistent total latency is observed across the JESD204B link and DAC analog channels.
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