Stratix® 10 Embedded Memory User Guide

ID 683423
Date 7/08/2024
Public
Document Table of Contents

4.4.5. FIFO2 Intel® FPGA IP Features

You can configure the FIFO2 Intel® FPGA IP core as either a DCFIFO or a SCFIFO by using the parameter editor of the FIFO2 Intel® FPGA IP core. When the FIFO2 Intel® FPGA IP core is configured as a SCFIFO, the relevant clock domain crossing (CDC) structure will not be synthesized.

The following figures show the timing diagrams for read and write operations for FIFO2 Intel® FPGA IP core.

Figure 50. Write to Full with Write Protection
Figure 51. Single Read with Read Protection