Stratix® 10 Embedded Memory User Guide

ID 683423
Date 3/29/2024
Public
Document Table of Contents

4.4.5.1. FIFO2 Specifications

The following table summarizes the specifications of the FIFO2 Intel® FPGA IP.
Table 58.  FIFO2 Specifications
Feature Storage Type
M20K MLAB
Error Checking and Correcting (ECC) Always 44 No
Read-out Interface

Analogy to Avalon® streaming non-zero readLatency.

For each r_req asserts now, r_valid shall indicate whether there is valid data to be taken (and must be taken) L clock later.

L = 6

Analogy to Avalon® streaming non-zero readLatency

For each r_req asserts now, r_valid shall indicate whether there is valid data to be taken (and must be taken) L clock later.

L = 5

Width (bits)

There is no hard limit on user data width but the internal RAM block is always in 32b x N; where N > 0.

Maximum = 4096b

Default to 1.

There is no hard limit on user data width but the internal RAM block is always in 20b x N; where N > 0.

Maximum = 4080b

Default to 1.

Depth 512 32
Depth Stitching No, user can cascade multiple FIFOs. No, user can cascade multiple FIFOs
Targeted Performance

Stratix® 10, bin1 production device.

32bx512: Up to 850 MHz

512bx512: Up to 700 MHz

Stratix® 10, bin1 production device.

20bx32: Up to 850 MHz

512bx32: Up to 700 MHz

Almost Full No, you can derive this from “Write Used”. No, you can derive this from “Write Used”.
Almost Empty No, you can derive this from “Read Used”. No, you can derive this from “Read Used”.
Read Used Yes, delayed RAM block words measurement excluding in-flight data. Yes, delayed RAM block words measurement excluding in-flight data.
Write Used Yes, delayed RAM block words measurement excluding in-flight data. Yes, delayed RAM block words measurement excluding in-flight data.
RAM with registered read output Always Always
Write full prevention Always, based on internal almost full. Always, based on internal almost full.
Read empty prevention Always Always
Output data initial states Unknown Unknown
Reset Scheme Contains non resettable flops, requires state flushing. Contains non resettable flops, requires state flushing.
RTL Encrypted Encrypted
44 In the FIFO2 Intel® FPGA IP, the ECC mode is embedded within the IP architecture and cannot be disabled. Unlike FIFO Intel® FPGA IP core, there is no ECCSTATUS signal that can be exported for use in your design.