Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022

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2.6.1. Forwarding Logic

In pipelining, you can use forwarding logic to perform data forwarding to reduce instruction cycles.

With coherent read feature and forwarding logic, you can coherently read out the data, perform operations (arithmetic or logical or both) on top of the data content, and write the data back to the same memory location within a single clock cycle.

Figure 11. Example Forwarding Logic with Simplified Coherent Read Memory Circuitry
Figure 12. Pipelining Waveform When Output of M20K Blocks is UnregisteredThis figure shows the waveform of the pipelining with the read enable (rden) signal is high.
Figure 13. Pipelining Waveform When Output of M20K Blocks is RegisteredThis figure shows the waveform of the pipelining with the write enable (wren) signal is high.

With the coherent read feature enabled and forwarding logic implemented, the output of M20K blocks can be either unregistered or registered. To match the latency of the coherency circuitry within the hardware boundary of the M20K blocks, you may need to manually add the additional pipeline registers on the wren and wraddress paths, which is described in the following table:

Table 8.  Pipeline Registers Requirements
Output Register Additional Pipeline Registers on wren and wraddress
Unregistered 0
Registered 1