Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022

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Document Table of Contents

2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks

The Intel® Stratix® 10 embedded memory blocks support byte enable controls.
  • The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
  • The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the embedded memory blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
  • The byte enable registers do not have a clear port.
  • The LSB of the byteena signal corresponds to the LSB of the data bus.
  • The byte enable signals are active high.
  • The byte width for the byte enable signal may differ depending on your selected memory block in the embedded memory IP parameter editors.