Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 4/25/2022
Public

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4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines

Use the following guidelines to provide a proper reset to the FIFO Intel® FPGA IP core:

  • Asynchronous clear is treated as a global IP reset event, and has the highest priority.
  • If both asynchronous clear and synchronous clear are implemented:
    • When asynchronous clear asserts, the associated synchronous clear (for the clock domain) must also be asserted.
    • Asynchronous clear must be deasserted first before synchronous clear (for the clock domain) deasserts. Use synchronous clear to control when the IP should be out of reset.
    • The asynchronous clear duration may be as short as 1 clock, but the synchronous clear must last for at least 32* slow clock cycles (clock must be toggling) to ensure all IP internal stale states are flushed.
  • If only asynchronous or synchronous clear is implemented, the clear assertion duration must last for at least 32* slow clock cycles (clock must be toggling) to ensure all IP internal stale states are flushed.
  • All clocks must be toggling valid for some time before asynchronous or synchronous clear deassertion.
  • As some reset signals are internally pipelined, write operations must not be started within 8* clocks after reset deassertion.
Figure 51. Reset BehaviorThis figure shows the reset behavior of the FIFO2 Intel® FPGA IP core.

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