AN 861: Intel® Stratix® 10 H-Tile PCI Express* Link Hardware Validation

ID 683407
Date 6/29/2018

1.2. Hardware Validation System Block Diagram

Figure 1. Hardware Validation System Simplified Block Diagram

The figure above shows the simplified block diagram of the hardware validation system. The Root Port in this system is the host PC, which interfaces with the PIO design example to perform memory reads and memory writes on an on-chip memory without the use of DMA.

The three main components of the design example are:

  1. Device-Under-Test (DUT): This refers to the PCIe* Hard IP (HIP), which you can configure.
  2. PIO Application: This takes in the Avalon® -ST data and converts it to the Avalon® -MM format before sending it to the slave.
  3. The slave in this case is an on-chip memory with a size that matches the DUT's BAR size.

For the host (or Root Port), a driver and application software are provided for the validation process. After the driver is installed, the hardware will be initialized and ready for transactions. Data is then packetized, and can be received by the DUT. In the validation process, the application software performs Memory Writes to the on-chip memory followed by Memory Reads from the on-chip memory. It then compares the written data with the read data. A matching dataset indicates a successful validation.