AN 861: Intel® Stratix® 10 H-Tile PCI Express* Link Hardware Validation

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ID 683407
Date 6/29/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation x
1.1. Overview 1.2. Hardware Validation System Block Diagram 1.3. Hardware and Software Requirements 1.4. Quick Start Guide 1.5. Document Revision History
1.3. Hardware and Software Requirements x
1.3.1. Hardware Requirements 1.3.2. Software Requirements
1.4. Quick Start Guide x
1.4.1. Hardware Setup 1.4.2. Running the Reference Design 1.4.3. Hardware Validation
1.4.2. Running the Reference Design x
1.4.2.1. Generating the Design 1.4.2.2. Compiling the Design Example and Programming the Device
1.4.3. Hardware Validation x
1.4.3.1. Hardware Validation on the Linux Platform 1.4.3.2. Hardware Validation on the Windows Platform
1.4.3.1. Hardware Validation on the Linux Platform x
1.4.3.1.1. Linux Kernel Driver 1.4.3.1.2. Installing the Linux Kernel Driver 1.4.3.1.3. Running the Design Example Application
1.4.3.2. Hardware Validation on the Windows Platform x
1.4.3.2.1. Installing the Windows driver 1.4.3.2.2. Running the Windows demo driver with design example
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation

1.4.3.1.3. Running the Design Example Application

  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application with the following command:

    $make

  3. Run the test with the following command:

    $ ./intel_fpga_pcie_link_test

By default, you can run the Intel FPGA IP PCIe* link test in manual or automatic mode. In this application note, the Intel FPGA IP PCIe* link test is run in automatic mode. The following figure shows an example of passing results with 0 write or read error.

Figure 8. Passing results for automatic mode with 0 write or read error
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