22.214.171.124. Generating the Design
- In the Intel® Quartus® Prime Pro Edition software, create a new project (go to File, and choose New Project Wizard).
- Specify the Directory, Name, and Top-Level Entity.
- For Project Type, accept the default value, Empty project. Click Next.
- For Add Files, click Next.
- For Family, Device & Board Settings, select Intel® Stratix® 10 for Family. Then select the Target Device for your design from the list of Available Devices.
- Click Finish.
- In the IP Catalog, locate and add the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* .
- In the New IP Variant dialogue box, specify a name for your IP.
- On the IP Settings tabs, specify the parameters for your IP variation.
- On the Example Designs tab, make the following selections:
- For Available Example Designs, select PIO.
- For Example Design Files, turn on the Simulation and Synthesis options.
- If you have selected a x16 configuration, for Select Simulation Root Complex BFM, choose the appropriate Bus Functional Model (BFM):
- Intel FPGA BFM: for all configurations up to Gen3 x8. This BFM supports x16 configurations by downtraining to x8.
- Third-party BFM: for x16 configurations if you want to simulate all 16 lanes. Refer to AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices for information about simulating with the Avery BFM.
- For Generated HDL Format, only Verilog is available in the current release.
- For Target Development Kit, select the appropriate option. Note: If you select None, the generated design example targets the device specified. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file.
- Select Generate Example Design to create a design example that you can simulate and download to hardware. If you select one of the Intel® Stratix® 10 development boards, the device on that board overwrites the device previously selected in the Intel® Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, accept the default directory, / pcie_s10_hip_ast_0_example_design.
Figure 4. Design Example Configuration
- Close the IP Parameter Editor followed by the project.
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