AN 861: Intel® Stratix® 10 H-Tile PCI Express* Link Hardware Validation

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ID 683407
Date 6/29/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation x
1.1. Overview 1.2. Hardware Validation System Block Diagram 1.3. Hardware and Software Requirements 1.4. Quick Start Guide 1.5. Document Revision History
1.3. Hardware and Software Requirements x
1.3.1. Hardware Requirements 1.3.2. Software Requirements
1.4. Quick Start Guide x
1.4.1. Hardware Setup 1.4.2. Running the Reference Design 1.4.3. Hardware Validation
1.4.2. Running the Reference Design x
1.4.2.1. Generating the Design 1.4.2.2. Compiling the Design Example and Programming the Device
1.4.3. Hardware Validation x
1.4.3.1. Hardware Validation on the Linux Platform 1.4.3.2. Hardware Validation on the Windows Platform
1.4.3.1. Hardware Validation on the Linux Platform x
1.4.3.1.1. Linux Kernel Driver 1.4.3.1.2. Installing the Linux Kernel Driver 1.4.3.1.3. Running the Design Example Application
1.4.3.2. Hardware Validation on the Windows Platform x
1.4.3.2.1. Installing the Windows driver 1.4.3.2.2. Running the Windows demo driver with design example
1. Intel® Stratix® 10 H-Tile PCIe* Link Hardware Validation

1.4.2.1. Generating the Design

  1. In the Intel® Quartus® Prime Pro Edition software, create a new project (go to File, and choose New Project Wizard).
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files, click Next.
  5. For Family, Device & Board Settings, select Intel® Stratix® 10 for Family. Then select the Target Device for your design from the list of Available Devices.
  6. Click Finish.
  7. In the IP Catalog, locate and add the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* .
  8. In the New IP Variant dialogue box, specify a name for your IP.
  9. On the IP Settings tabs, specify the parameters for your IP variation.
  10. On the Example Designs tab, make the following selections:
    1. For Available Example Designs, select PIO.
    2. For Example Design Files, turn on the Simulation and Synthesis options.
    3. If you have selected a x16 configuration, for Select Simulation Root Complex BFM, choose the appropriate Bus Functional Model (BFM):
      • Intel FPGA BFM: for all configurations up to Gen3 x8. This BFM supports x16 configurations by downtraining to x8.
      • Third-party BFM: for x16 configurations if you want to simulate all 16 lanes. Refer to AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices for information about simulating with the Avery BFM.
    4. For Generated HDL Format, only Verilog is available in the current release.
    5. For Target Development Kit, select the appropriate option. Note: If you select None, the generated design example targets the device specified. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file.
  11. Select Generate Example Design to create a design example that you can simulate and download to hardware. If you select one of the Intel® Stratix® 10 development boards, the device on that board overwrites the device previously selected in the Intel® Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, accept the default directory, / pcie_s10_hip_ast_0_example_design.
    Figure 4. Design Example Configuration
  12. Close the IP Parameter Editor followed by the project.
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