AN 861: Intel® Stratix® 10 H-Tile PCI Express* Link Hardware Validation

ID 683407
Date 6/29/2018

1.1. Overview

The Intel® Stratix® 10 Hard IP for PCI Express* IP core includes a programmed I/O (PIO) design example to help you understand the usage for this IP. The PIO design example transfers data from the host memory to the local memory on a target device, which in this case is an Intel FPGA. This design example is appropriate for low-bandwidth applications. In the PCIe* link hardware validation process, this design example serves as an Endpoint (EP) that interacts with the host, which is the Root Port. The same design example can be used in your hardware to validate if a PCIe* link is working as expected. The Intel® Stratix® 10 GX FPGA Development Kit with H-Tile device is used in the hardware validation process. This validation is performed on both the Linux* and Windows* platforms.