JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 11/22/2021
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3.1.3. SPI Master

The SPI master module is a standard Platform Designer component in the IP Catalog standard library. This module uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, and external clock generators) via a structured register space inside these devices. The SPI master has an Avalon® memory-mapped interface that connects to the Avalon® master (JTAG to Avalon® master bridge) via the Avalon® memory-mapped interconnect. The SPI master receives configuration instructions from the Avalon® master.

The SPI master module controls up to 32 independent SPI slaves. The SCLK baud rate is configured to 20 MHz (divisible by 5).

This module is configured to a 4-wire, 24-bit width interface. If the Generate 3-Wire SPI Module option is selected, an additional module is instantiated to convert the 4-wire output of the SPI master to 3-wire.

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