JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683357
Date 11/22/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

3.4. JESD204C Design Example Control Registers

The JESD204C design example registers in the ED Control block use byte-addressing (32 bits).
Table 17.  Design Example Address MapThese 32-bit ED Control block registers are in the mgmt_clk domain.
Component Address
ED Control 0x0102_0400 – 0x0102_04FF
MM Bridge 0x0000_0000 – 0x007F_FFFF
PIO Control 0x0102_0020 – 0x0102_002F
PIO Status 0x0102_0040 – 0x0102_004F
Reset Sequencer 0 0x0102_0100 – 0x0102_01FF
Reset Sequencer 1 0x0102_0200 – 0x0102_02FF
SPI Control 0x0102_0000 – 0x0102_001F
JESD204C IP transceiver PHY Reconfig 0x0200_0000 – 0x020F_FFFF (2-lane transceiver PHY)
0x0200_0000 – 0x021F_FFFF (4-lane transceiver PHY)
JESD204C TX IP (Link 0) 0x000C_0000 – 0x000C_03FF
JESD204C RX IP (Link 0) 0x000D_0000 – 0x000D_03FF
Table 18.  Register Access Type and DefinitionThis table describes the register access type for Intel® FPGA IPs.
Access Type Definition
RO/V Software read-only (no effect on write). The value may vary.
RW
  • Software reads and returns the current bit value.
  • Software writes and sets the bit to the desired value.
RW1C
  • Software reads and returns the current bit value.
  • Software writes 0 and has no effect.
  • Software writes 1 and clears the bit to 0 if the bit has been set to 1 by hardware.
  • Hardware sets the bit to 1.
  • Software clear has higher priority than hardware set.
Table 19.  ED Control Block Control and Status Registers
Byte Offset Register Name Access Reset Description
0x00 rst_ctl rst_assert RW 0x0 Reset control.

[0]: Assert software global reset at mgmt_rst_in_n by writing 1 to this bit. Write 0 to this bit to deassert global reset..

[31:1]: Reserved.

0x04 rst_sts0 rst_status RO/V 0x0

Reset status.

[0]: Core PLL locked status.

[31:1]: Reserved.
0x08 rst_sts1 RO/V 0x0

Reset status.

[15:0]: tx_pma_ready status for TX lane 0 to lane 15. LSB for TX lane 0.

[31:16]: rx_pma_ready status for RX lane 0 to lane 15. Bit 16 for RX lane 0.

0x0c rst_sts2 RO/V 0x0

Reserved.
0x10 rst_sts_detected0 rst_sts_set RW1C 0x0

SYSREF edge detection status for internal or external SYSREF generator.

[0]: Value of 1 Indicates a SYSREF rising edge is detected for subclass 1 operation. Software may write 1 to clear this bit to enable new SYSREF edge detection.

[31:1]: Reserved.

0x14 rst_sts_detected1 RW1C 0x0 Reserved.
0x40 sysref_ctl sysref_control RW

Duplex datapath

  • One-shot: 0x00080
  • Periodic: 0x00081
  • Gapped-periodic: 0x00082

TX or RX data path

  • One-shot: 0x00000
  • Periodic: 0x00001
  • Gapped-periodic: 0x00002

SYSREF control.

Refer to Table 11 for more information about the usage of this register.
Note: The reset value depends on the SYSREF type and JESD204C IP data path parameter settings.
0x44 sysref_sts sysref_status RO/V 0x0

SYSREF status. This register contains the latest SYSREF period and duty cycle settings of the internal SYSREF generator.

Refer to Table 10 for the legal value of the SYSREF period and duty cycle.

[7:0]: SYSREF period.

  • When the value is 0xFF, the SYSREF period = 255.
  • When the value if 0x00, the SYSREF period = 256.

[15:8]: SYSREF duty cycle.

[31:16]: Reserved.
0x80 tst_ctl tst_control RW 0x0

Test control. Use this register to enable different test patterns for the pattern generator and checker.

[1:0] = Reserved field

[2] = ramp_test_ctl

  • 1’b0 = Enables PRBS pattern generator and checker
  • 1’b1 = Enables ramp pattern generator and checker

[31:3]: Reserved.
0x84 tst_sts0 tst_status RW1C 0x0

Reserved.
0x88 tst_sts1 RW1C 0x0

Reserved.
0x8c tst_err0 tst_error RW1C 0x0

Error flag for Link 0. When the bit is 1’b1, it indicates an error has happened. You should resolve the error before writing 1’b1 to the respective bit to clear the error flag.

[0] = Pattern checker error

[1] = tx_link_error

[2] = rx_link_error

[3] = Command pattern checker error

[31:4]: Reserved.
0x90 tst_err1 RW1C 0x0

Reserved.
Level Two Title