||Updated Compiling and Testing the Design to include related information about running the hardware testing using the Tcl script.
||Updated the JESD204C Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide chapter:
- Added support for Questa* simulator.
- Removed references to the NCSim simulator.
- Updated the Compiling and Testing the Design and Board Connectivity sections with the latest information for design examples with bonded and non-bonded mode configurations.
- Removed the Clock Control GUI column in Table: Clock Settings.
- Updated the change in board information for Intel® Stratix® 10 E-tile devices in the Compiling and Testing the Design and Board Connectivity sections.
- Updated the Compiling and Testing the Design section with new information about the clock settings.
- Updated the Board Connectivity section with latest information for the refclk_core and mgmt_clk ports.
- Updated the description for the tst_ctl register in the JESD204C Design Example Control Registers section and the Test pattern parameter in the Design Example Parameters section. Starting Intel® Quartus® Prime Pro Edition software version 19.3 onwards, you can no longer use the [1:0] bit of the test control register to change the PRBS pattern. Use the Test pattern parameter instead.
- Updated the related document links and the acronyms, glossary, and symbols lists in the About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide section.
- Updated the files and folders in the Directory Structure section.
- Added an alternative command for the ModelSim* simulator in the Compiling and Simulating the Design section.
- Edited the JESD204C design example block diagram to remove multilink implementation the Design Example Block Diagram section. Multilink implementation will be supported in a future release.
- Edited the information in the following sections for better clarity.
- JTAG to Master Bridge
- Parallel I/O (PIO) Core
- SPI Master
- SYSREF Generator
- Pattern Generator and Checker
- Edited the descriptions and the timing diagram for the design example clocks and resets in the JESD204C Design Example Clock and Reset section.
- Edited the descriptions for the design example registers in the JESD204C Design Example Control Registers section.