JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 11/22/2021

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2.1. Design Example Block Diagram

Figure 2.  JESD204C Design Example High-level Block Diagram

The design example consists of the following modules:

  • Platform Designer system
    • JESD204C Intel® FPGA IP
    • JTAG to Avalon master bridge
    • Parallel I/O (PIO) controller
    • Serial Port Interface (SPI)—master module
    • Core PLL
    • SYSREF generator
  • Pattern generator
  • Pattern checker
Table 5.  Design Example Modules
Components Description
Platform Designer system

The Platform Designer system instantiates the JESD204C IP data path and supporting peripherals.

JESD204C Intel® FPGA IP This Platform Designer subsystem contains the TX and RX JESD204C IPs instantiated together with the duplex PHY.

JTAG to Avalon Master bridge

This bridge provides system console host access to the memory-mapped IP in the design through the JTAG interface.

Parallel I/O (PIO) controller

This controller provides a memory-mapped interface for sampling and driving general purpose I/O ports.

SPI master

This module handles the serial transfer of configuration data to the SPI interface on the converter end.

SYSREF generator

The SYSREF generator uses the link clock as a reference clock and generates SYSREF pulses for the JESD204C IP.

Note: This design example uses the SYSREF generator to demonstrate the duplex JESD204C IP link initialization. In the JESD204C subclass 1 system level application, you must generate the SYSREF from the same source as the device clock.

Pattern generator

The pattern generator generates a PRBS or ramp pattern.

Pattern checker

The pattern checker verifies the PRBS or ramp pattern received, and flags an error when it finds a mismatch of data sample.


This design example uses an IOPLL to generate a user clock for transmitting data into the JESD204C IP.