JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 11/22/2021
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3.5.1. Board Connectivity

If you are performing hardware testing on the selected Intel development kits, generate the design example with the appropriate target development kit selected.

Refer to the instructions in Generating the Design.

Note: Running the hardware test with the design generated as-is is only possible when the JESD204C Intel® FPGA IP is configured in duplex data path mode (i.e. with both TX and RX data paths present). Make your own modifications to the design to run the hardware test if generating a simplex data path design.
Table 21.   Intel® Stratix® 10 TX Signal Integrity Development Kit Board ConnectivityThe generated design has pre-assigned pins that target the relevant boards. The table describes the board connectivity of key design ports for all supported target development kits.
Port Name Port Description Board Component Component Description
global_rst_n Global reset

S8

S8 push-button

refclk_core Core PLL reference clock input

U3

Si5341 clock generator (OUT3)

refclk_xcvr Transceiver reference clock input Engineering sample version board revision A (non-bonded channels) and Production version board revision B (non-bonded channels)

U3

Si5341 clock generator (OUT8)

Production version board revision B (bonded channels)

U3

Si5341 clock generator (OUT4)

mgmt_clk Control clock

U3

Si5341 clock generator (OUT2) (100 MHz)

tx_serial_data TX serial data Engineering sample version board revision A (non-bonded, up to 8 channels)

U32-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Engineering sample version board revision A (non-bonded, 9–16 channels)

U32-1 and U75-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Production version board revision B (non-bonded, up to 16 channels)

J27D

Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)
Production version board revision B (bonded, up to 4 channels)

U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)
Production version board revision B (bonded, 5–8 channels)

U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)
rx_serial_data RX serial data Engineering sample version board revision A (non-bonded, up to 8 channels)

U32-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)

Engineering sample version board revision A (non-bonded, 9–16 channels)

U32-1 and U75-1

Intel® Stratix® 10 E-tile banks - 8B (QSFP-DD 1x2)
Production version board revision B (non-bonded, up to 16 channels)

J27D

Intel® Stratix® 10 E-tile banks – 8B (FMC+ connector)
Production version board revision B (bonded, up to 4 channels)

U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)
Production version board revision B (bonded, 5–8 channels)

U32-1 and U75-1

Intel® Stratix® 10 E-tile banks – 9C (QSFP-DD 1x2 connector)
user_led[0] GPIO- SPI programming done

U39G

Banks 2 L/M/N ( G31)

user_dip[0] GPIO- internal serial loopback enable

U39G

Banks 2 L/M/N ( G23)

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