JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 11/22/2021

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3.1.1. JTAG to Avalon® Master Bridge

The JTAG to Avalon® Master Bridge provides a connection between the host system to access the memory-mapped JESD204C IP and the peripheral IP control and status registers through the JTAG interface.

Figure 7. System with a JTAG to Avalon® Master Bridge Core
Note: System clock must be at least 2X faster than the JTAG clock. The system clock is mgmt_clk (100MHz) in this design example.