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1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
3.1.2. Parallel I/O (PIO) Core
The parallel input/output (PIO) core with Avalon® interface provides a memory-mapped interface between an Avalon® memory-mapped slave port and general purpose I/O ports. The I/O ports connect either to on-chip user logic, or to I/O pins that connect to devices external to the FPGA.
Figure 8. PIO Core with Input Ports, Output Ports, and IRQ SupportBy default, the Platform Designer component disables the Interrupt Service Line (IRQ).
The PIO I/O ports are assigned at the top level HDL file (io_status for input ports, io_control for output ports).
The table below describes the signal connectivity for the status and control I/O ports to the DIP switch and LED on the development kit.
|Out_port||0||USER_LED SPI programming done|
|In_port||0||USER_DIP internal serial loopback enable
Off = 1
On = 0
|1||USER_DIP FPGA-generated SYSREF enable
Off = 1
On = 0
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