JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 11/22/2021
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3.1.2. Parallel I/O (PIO) Core

The parallel input/output (PIO) core with Avalon® interface provides a memory-mapped interface between an Avalon® memory-mapped slave port and general purpose I/O ports. The I/O ports connect either to on-chip user logic, or to I/O pins that connect to devices external to the FPGA.

Figure 8. PIO Core with Input Ports, Output Ports, and IRQ SupportBy default, the Platform Designer component disables the Interrupt Service Line (IRQ).

The PIO I/O ports are assigned at the top level HDL file (io_status for input ports, io_control for output ports).

The table below describes the signal connectivity for the status and control I/O ports to the DIP switch and LED on the development kit.

Table 9.  PIO Core I/O Ports
Port Bit Signal
Out_port 0 USER_LED SPI programming done
31:1 Reserved
In_port 0 USER_DIP internal serial loopback enable

Off = 1

On = 0

1 USER_DIP FPGA-generated SYSREF enable

Off = 1

On = 0

31:2 Reserved.

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