Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 3/28/2022
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11.4.1.4.2. XML Elements for INTERFACE

In the RTL module properties file of the RTL module within an HLS library, there are XML elements under INTERFACE that define aspects of the RTL module interface.

The RTL module cannot access the memories of the HLS component.

Table 31.  Mandatory XML Elements for the RTL module properties file INTERFACE Element
XML Element Description
INPUT

Specifies the input parameter of the RTL module that receives the value of a call argument with the RTL-based function is called.

INPUT attributes:

  • port

    Specifies the port name of the RTL module.

  • width

    Specifies the width of the port in bits.

All call arguments must be passed by value. You cannot use reference, pointer, and array type arguments.

OUTPUT

Specifies the output parameter of the RTL module that represents the return value of functions based on this module.

OUTPUT attributes:

  • port

    Specifies the port name of the RTL module.

  • width

    Specifies the width of the port in bits.

    The width of the port must match the size of the C datatype of the function return value. The port width is always a multiple of 8 bits.

The return value cannot be a pointer.

STREAM Specifies the stream parameters to the RTL module.
STREAM attributes:
  • port

    Specifies the base port name for the stream input to the RTL module.

  • width

    Specifies the width of the port in bits.

  • direction

    Specifies the streaming direction.

    Valid values for the direction attribute are in and out. Use direction="in" for streams that are read by the RTL module and direction="out" for streams that written to by the RTL module.

  • buffer

    Specifies the size of the stream buffer in words.

    The default value is buffer="0".

  • usesValid

    Specifies whether this RTL module uses the valid signal for the stream interface.

    The default value is usesValid="no"

  • usesReady

    Specifies whether this RTL module uses the ready signal for the stream interface.

    The default value is usesReady="no"

  • usesEmpty

    Specifies whether this RTL module uses the empty signal for the stream interface.

    The default value is usesEmpty="no".

  • usesPackets

    Specifies whether this RTL module uses the packet signals for the stream interface.

    The default value is usesPackets="no".

  • firstSymbolInHighOrderBits

    Specifies whether the data symbols in the stream are in big endian order.

    The default value is firstSymbolInHighOrderBits="no".

  • bitsPerSymbol

    Specifies how the data is broken into symbols on the data bus.

    The default value is bitsPerSymbol="0".

  • readyLatency

    Specifies the number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs.

    The default value is readyLatency="0".

The values you specify here must match the values for the stream object input interface parameters in your component. For details about stream input interface parameters in your component, see Intel HLS Compiler Pro Edition Streaming Input Interfaces.

The signal names in your RTL and your component code must align. For details, seeMapping HLS Data Types to RTL Signals.

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