Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 3/28/2022
Public

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13.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces

Use the mm_host object and template arguments to explicitly declare Avalon® Memory-Mapped (MM) Host interfaces for your component.

Table 57.   Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces Summary
Template Object or Parameter Description
ihc::mm_host The underlying pointer type.
ihc::dwidth The width of the memory-mapped data bus in bits
ihc::awidth The width of the memory-mapped address bus in bits.
ihc::aspace The address space of the interface that associates with the host.
ihc::latency The guaranteed latency from when a read command exits the component when the external memory returns valid read data.
ihc::maxburst The maximum number of data transfers that can associate with a read or write transaction.
ihc::align The alignment of the base pointer address in bytes.
ihc::readwrite_mode The port direction of the interface.
ihc::waitrequest

Adds the waitrequest signal that is asserted by the agent when it is unable to respond to a read or write request.

getInterfaceAtIndex This testbench function is used to index into an mm_host object.

ihc::mm_host Template Object

Syntax
ihc::mm_host<datatype, template parameter >
Valid values
Any valid C++ datatype
Default Value
Default interface for pointer arguments.
Description
The underlying pointer type. Pointer arithmetic performed on the host object conforms to this type. Dereferences of the host results in a load-store site with a width of sizeof(datatype). The default alignment is aligned to the size of the datatype.

You can use multiple template arguments in any combination as long the combination of arguments describes a valid hardware configuration.

Example:
component int dut(
 ihc::mm_host<int, 
   ihc::aspace<2>, ihc::latency<3>,
   ihc::awidth<10>, ihc::dwidth<32>
  > &a)
To learn more, review the following tutorials:
  • <quartus_installdir>/hls/examples/tutorials/interfaces/pointer_mm_host
  • <quartus_installdir>/hls/examples/tutorials/interfaces/mm_host_testbench_operators

ihc::dwidth Template Parameter

Syntax
ihc::dwidth<value>
Valid Values
8, 16, 32, 64, 128, 256, 512, or 1024
Default Value
64
Description
The width of the memory-mapped data bus in bits.

ihc::awidth Template Parameter

Syntax
ihc::awidth<value>
Valid Values
Integer value in the range 1 – 64
Default Value
64
Description
The width of the memory-mapped address bus in bits.

This value affects only the width of the Avalon® MM Host interface. The size of the conduit of the base address pointer is always set to 64-bits.

ihc::aspace Template Parameter

Syntax
ihc::aspace<value>
Valid Values
Integer value greater than 0.
Default Value
1
Description
The address space of the interface that associates with the host. Each unique value results in a separate Avalon MM Host interface on your component. All hosts with the same address space are arbitrated within the component to a single interface. As such, these hosts must share the same template parameters that describe the interface.

ihc::latency Template Parameter

Syntax
ihc::latency<value>
Valid Values
Non-negative integer value
Default Value
1
Description
The guaranteed latency from when a read command exits the component when the external memory returns valid read data. If this latency is variable (such as when accessing DRAM), set it to 0.

ihc::maxburst Template Parameter

Syntax
ihc::maxburst<value>
Valid Values
Integer value in the range 1 – 1024
Default Value
1
Description
The maximum number of data transfers that can associate with a read or write transaction. This value controls the width of the burstcount signal.

For fixed latency interfaces, this value must be set to 1.

For more details, review information about burst signals and the burstcount signal role in "Avalon Memory-Mapped Interface Signal Roles" in Avalon Interface Specifications.

ihc::align Template Parameter

Syntax
ihc::align<value>
Valid Values
Integer value greater than the alignment of the datatype
Default Value
Alignment of the datatype
Description
The alignment of the base pointer address in bytes.

The Intel® HLS Compiler uses this information to determine how many simultaneous loads and stores this pointer can permit.

For example, if you have a bus with 4 32-bit integers on it, you should use ihc::dwidth<128> (bits) and ihc::align<16> (bytes). This means that up to 16 contiguous bytes (or 4 32-bit integers) can be loaded or stored as a coalesced memory word per clock cycle.

Important: The caller is responsible for aligning the data to the set value for the align argument; otherwise, functional failures might occur.

ihc::readwrite_mode Template Parameter

Syntax
ihc::readwrite_mode<value>
Valid Values
readwrite, readonly, or writeonly
Default Value
readwrite
Description
The port direction of the interface. Only the relevant Avalon host signals are generated.

ihc::waitrequest Template Parameter

Syntax
ihc::waitrequest<value>
Valid Values
true or false
Default Value
false
Description
Adds the waitrequest signal that is asserted by the agent when it is unable to respond to a read or write request. For more information about the waitrequest signal, see "Avalon Memory-Mapped Interface Signal Roles" in Avalon Interface Specifications.

getInterfaceAtIndex Testbench Function

Syntax
getInterfaceAtIndex(int index)
Description
This testbench function is used to index into an mm_host object. It can be useful when iterating over an array and invoking a component on different indicies of the array. This function is supported only in the testbench.
Code Example
int main() {
// …….
for(int idx = 0; idx < N; idx++) {
  dut(src_mm.getInterfaceAtIndex(idx));
}
// …….
}

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