Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 3/28/2022
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13.6. Intel® HLS Compiler Pro Edition Component Memory Attributes

Use the component memory attributes to control the on-chip component memory architecture of your component.

Table 42.   Intel® HLS Compiler Pro Edition Component Memory Attributes Summary
Memory Attribute Description
hls_force_pow2_depth Specifies that the memory implementing the variable or array has power-of-2 depth.
hls_register Forces a variable or array to be carried through the pipeline in registers.

A register variable can be implemented either exclusively in flip-flops (FFs) or in a mix of FFs and RAM-based FIFOs.

hls_memory Forces a variable or array to be implemented as embedded memory.
hls_memory_impl Forces a variable or array to be implemented as embedded memory of a specified type.
hls_singlepump Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.
hls_doublepump Specifies that the memory implementing the variable or array must be clocked at twice the rate as the component accessing the memory.
hls_numbanks Specifies that the memory implementing the variable or array must have a defined number of memory banks.
hls_bankwidth Specifies that the memory implementing the variable or array must have memory banks of a defined width.
hls_bankbits Forces the memory system to split into a defined number of memory banks and defines the bits used to select a memory bank.
hls_simple_dual_port_memory Specifies that the memory implementing the variable or array should have no port that services both reads and writes.
hls_merge (depthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.
hls_merge (widthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.
hls_init_on_reset Forces the static variables inside the component to be initialized when the component reset signal is asserted.
hls_init_on_powerup Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed.
hls_max_concurrency
Deprecated: This attribute is deprecated and will be removed in a future release. Use the hls_private_copies memory attribute instead.
Specifies that the memory implementing the variable or array has a defined number of private copies to allow concurrent iterations of a loop at any given time.
hls_max_replicates Specifies that the memory implementing the variable or array has no more than the specified number of replicates to enable simultaneous reads from the datapath
hls_private_copies Specifies that the memory implementing the variable or array has a defined number of private copies to allow concurrent iterations of a loop at any given time.

hls_force_pow2_depth Memory Attribute

Syntax
hls_force_pow2_depth(N)
Constraints
N can be only 0 or 1.
Default Value
1
Description
Specifies that the memory implementing the variable or array has a power-of-2 depth. This option is enabled if N is 1, and disabled if N is 0.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/non_power_of_two_memory.

hls_register Memory Attribute

Syntax
hls_register
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as registers.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/swap_vs_copy.

hls_memory Memory Attribute

Syntax
hls_memory
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as embedded memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_implementation.

hls_memory_impl Memory Attribute

Syntax
hls_memory_impl("type")
Constraints
N/A
Default Value
Based on the memory size and memory access pattern inferred by the compiler.
Description

Forces a variable or array to be implemented as embedded memory of the specified type.

The type parameter can be one of the following values:
BLOCK_RAM
Implement the variable or array as memory blocks, such as M20K memory blocks.
MLAB
Implement the variable or array as memory logic array blocks (MLABs).

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_implementation.

hls_singlepump Memory Attribute

Syntax
hls_singlepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/QRD.

hls_doublepump Memory Attribute

Syntax
hls_doublepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at twice the rate of the component accessing the memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_numbanks Memory Attribute

Syntax
hls_numbanks(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have N banks, where N is a power-of-two constant number.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_bankwidth Memory Attribute

Syntax
hls_bankwidth(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have banks that are N bytes wide, where N is a power-of-two constant number.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_bankbits Memory Attribute

Syntax
hls_bankbits(b 0 , b 1 , ..., b n )
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces the memory system to split into 2n+1 banks, with {b 0 , b 1 , ..., b n } forming the bank-select bits.
Important: b 0 , b 1 , ..., b n must be consecutive, positive integers. You can specify the consecutive, positive integers in ascending or descending order.

If you do not specify the hls_bankwidth(N) attribute along with this attribute, then b 0 , b 1 , ..., b n are mapped to array index bits 0 to n-1 in the memory bank implementation.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_simple_dual_port_memory Memory Attribute

Syntax
hls_simple_dual_port_memory
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array should have no port that services both reads and writes.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_merge (depthwise) Memory Attribute

Syntax
hls_merge("mem_name", "depth")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_merging.

hls_merge (widthwise) Memory Attribute

Syntax
hls_merge("mem_name", "width")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_merging.

hls_init_on_reset Memory Attribute

Syntax
hls_init_on_reset
Constraints
N/A
Default Value
Default behavior for static variables.
Description
Forces the static variable inside the component to be initialized when the component reset signal is asserted. This requires an additional write port to the component memory implemented and can increase the power-up latency when the component is reset.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_init_on_powerup Memory Attribute

Syntax
hls_init_on_powerup
Constraints
N/A
Default Value
N/A
Description
Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed. When the component is reset, the component memory is not reset back to the initialized value of the static.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_max_concurrency Memory Attribute

Deprecated: This attribute is deprecated and will be removed in a future release. Use the hls_private_copies memory attribute instead.
Syntax
hls_max_concurrency(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has N private copies to allow N concurrent iterations of a loop at any given time.

Apply this attribute only when the scope of a variable (through its declaration or access pattern) is limited to a loop. If the loop has the max_concurrency pragma applied to it, the number of private copies created is the lesser of the hls_max_concurrency memory attribute value and the max_concurrency pragma value.

hls_max_replicates Memory Attribute

Syntax
hls_max_replicates(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has no more than the N replicates to enable simultaneous reads from the datapath.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_private_copies Memory Attribute

Syntax
hls_private_copies(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has N private copies to allow N concurrent iterations of a loop at any given time.

Apply this attribute only when the scope of a variable (through its declaration or access pattern) is limited to a loop. If the loop has the max_concurrency pragma applied to it, the number of private copies created is the lesser of the hls_private_copies memory attribute value and the max_concurrency pragma value.

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