Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 3/28/2022
Public

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11.4.1.4. Object Manifest File Syntax

The HLS library object manifest file is an XML file that maps the RTL modules in a library object to functions that can be called by your HLS code. The Intel® HLS Compiler uses the properties defined in the manifest file to integrate an RTL module into the component pipeline.

The following example show a simple object manifest file for an RTL module that implements a double-precision square root function. The RTL module is implemented in VHDL with a Verilog wrapper.

The following object manifest file is for an RTL module named my_fp_sqrt_double (line 2) that implements a callable function with a C interface named my_sqrtfd (line 2).

 1: <RTL_SPEC>
 2:   <FUNCTION name="my_sqrtfd" module="my_fp_sqrt_double">
 3:     <ATTRIBUTES>  
 4:       <IS_STALL_FREE value="yes"/>
 5:       <IS_FIXED_LATENCY value="yes"/>
 6:       <EXPECTED_LATENCY value="31"/>
 7:       <CAPACITY value="31"/>
 8:       <HAS_SIDE_EFFECTS value="no"/>
 9:       <ALLOW_MERGING value="no"/>
10:       <PARAMETER name="WIDTH" value="64"/>
11:     </ATTRIBUTES> 
12:     <INTERFACE>
13:       <AVALON port="clock" type="clock"/>
14:       <AVALON port="resetn" type="resetn"/>
15:       <AVALON port="ivalid" type="ivalid"/>
16:       <AVALON port="iready" type="iready"/>
17:       <AVALON port="ovalid" type="ovalid"/>
18:       <AVALON port="oready" type="oready"/>
19:       <INPUT port="datain" width="64"/>
20:       <OUTPUT port="dataout" width="64"/>
21:     </INTERFACE>
22:     <REQUIREMENTS>
23:       <FILE name="my_fp_sqrt_double_s5.v" />
24:       <FILE name="fp_sqrt_double_s5.vhd" />
25:     </REQUIREMENTS>
26:     <RESOURCES>
27:       <ALUTS value="2057"/>
28:       <FFS value="3098"/>
29:       <RAMS value="15"/>
30:       <MLABS value="43"/>
31:       <DSPS value="1.5"/>
32:     </RESOURCES>
33:   </FUNCTION>
34: </RTL_SPEC>
Table 28.  Elements and Attributes in the Object Manifest File
XML Element Description
RTL_SPEC Top-level element in the object manifest file. There can only be one such top-level element in the file.
FUNCTION

Element that defines the HLS function that the RTL module implements. The name attribute within the FUNCTION element specifies the function name.

You might have multiple FUNCTION elements, each declaring a different function that you can call from the HLS component.

The same RTL module can implement multiple functions by specifying different parameters. To use the same module with different parameter combinations, create a separate FUNCTION tag for each parameter combination.

ATTRIBUTES Element that contains other XML elements that describe various characteristics (for example, latency) of the RTL module.

The example RTL module takes one PARAMETER setting named WIDTH, which has a value of 64.

See XML Elements for ATTRIBUTES for more details other ATTRIBUTES-specific elements.

If you create multiple RTL-based functions using different modules or use the same RTL module with different PARAMETER settings, you must create a separate FUNCTION element for each function.

INTERFACE Element that contains other XML elements that describe the RTL module interface.

The example object manifest file shows the streaming interface signals that every RTL module must provide (that is, clock, resetn, ivalid, iready, ovalid, and oready).

The resetn signal is active low. Its synchronicity depends on the target device:
Intel® Agilex™
The resetn signal is synchronous to the clock signal. For more information about reset signal timing, see Intel Agilex and Intel Stratix 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules.
Intel® Arria® 10
The resetn signal is asynchronous to the clock signal.
Intel® Stratix® 10
The resetn signal is synchronous to the clock signal. For more information about reset signal timing, see Intel Agilex and Intel Stratix 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules.

The signal names must match the ones specified in the RTL module properties file. An error occurs during library creation if a signal name is different in the RTL code and the RTL module properties file.

REQUIREMENTS Element that specifies one or more RTL resource files (that is, .v, .sv, .vhd, .hex, and .mif). The specified paths to these files are relative to the location of the object manifest file. Each RTL resource file becomes part of the associated Platform Designer component that corresponds to the entire HLS component.

HLS libraries do not support .qip files.

RESOURCES Optional element that specifies an estimate of the FPGA resources that the RTL module uses. If you do not specify this element, the estimated FPGA resources that the RTL module uses defaults to zero in the HLS resource estimation report.

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