AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

ID 683344
Date 12/14/2015
Public

1.3.2. Ethernet Packet Monitor Configuration Registers

Table 10.  Ethernet Packet Monitor Configuration Registers
Byte Offset Register Bit Number Bit Name R/W H/W Reset Description
0x00 number_packet 31:0 RO 0x00 Total number of packets the monitor expects to receive.
0x04 packet_rx_ok 31:0 RO 0x00 Total number of good packets received.
0x08 packet_rx_error 31:0 RO 0x00

Total number of packets received with error.

0x0C byte_rx_count_0 31:0 RO 0x00

64-bit counter that keeps track of the total number of bytes received.

  • byte_rx_count_0 represents the lower 32 bits.
  • byte_rx_count_1 represents the upper 32 bits.

Read byte_rx_count_0 followed by byte_rx_count_1 in the subsequent cycle to get an accurate count.

0x10 byte_rx_count_1 31:0 RO 0x00
0x14 cycle_rx_count_0 31:0 RO 0x00

64-bit counter that keeps track of the total number of cycles the monitor takes to receive all packets..

  • cycle_rx_count_0 represents the lower 32 bits.
  • cycle_rx_count_1 represents the upper 32 bits.

Read byte_rx_count_0 followed by byte_rx_count_1 in the subsequent cycle to get an accurate count.

0x18 cycle_rx_count_1 31:0 RO 0x00
0x1C rx_control_status 0 START RW 0x00 Set this bit to 1 to start packet reception. This bit clears when packet reception starts.
1 STOP RW 0x00 Set this bit to 1 to stop packet reception. This bit clears each time packet reception starts.
2 RX_DONE RO 0x00 A value of 1 indicates that the packet monitor has received the total number of packets specified in the number_packet register.
3 CRCBAD RO 0x00

A value of 1 indicates CRC error in the current packet received by the monitor.

9:4 RX_ERR RO 0x00

Receive error status.

The rx_err[] signal of the Triple-Speed Ethernet IP core maps to this register.

31:10

Reserved.