AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

1.3.1. Ethernet Packet Generator Configuration Registers

Table 9.  Ethernet Packet Generator Configuration Registers
Byte Offset Register Bit Number Bit Name R/W H/W Reset Description
0x00 number_packet 31:0 – RW 0x00 Specifies the total number of packets to be generated.
0x04 config_setting 0 LENGTH_SEL RW 0x00

0: Fixed packet length

1: Random packet length
14:1 PKT_LENGTH RW 0x00

Specifies the fixed packet length.

Valid values are between 24 to 9,600.

Applicable only when you set bit 0 of this register to 0.
15 PATTERN_SEL RW 0x00

Specifies the data pattern for the random packet length.

0: Incremental—data starts from zero and increments by 1 in subsequent bytes.

1: Random.
31:16 – – – Reserved.
0x08 operation 0 START RW 0x00 Set this bit to 1 to trigger packet generation. This bit clears as soon as packet generation starts.
1 STOP RW 0x00 Set this bit to 1 to stop packet generation. The generator completes the current packet before termination packet generation.
2 TX_DONE RO 0x00 A value of 1 indicates that the packet generator completes generating the total number of packets specified in the number_packet register. This bit clears each time packet generation triggers.
31:3 – – –

Reserved.
0x10 source_addr0 31:0 – RW 0x00
6-byte MAC address.
  • source_addr0/destination_addr0 = last four bytes of the address
  • Bits 0 to 15 of source_addr1/destination_addr1 = first two bytes of the address
  • Bits 16 to 31 of source_addr1/destination_addr1 = unused
For example, if the source MAC address is 00-1C-23-17-4A-CB, you get the following assignments:
  • source_addr0 = 0x17231C00
  • source_addr1 = 0x0000CB4A
0x14 source addr1 31:0 – RW 0x00
0x18 destination_addr0 31:0 – RW 0x00
0x1C destination_addr1 31:0 – RW 0x00
0x24 packet_tx_count 31:0 – – –

Keeps track of the number of packets the generator successfully transmits. This register clears each time packet generation triggers.

0x30 rand_seed0 31:0 – RW 0x00

The lower 32 bits of the random seed.

Occupies bits 31:0 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register).

0x34 rand_seed1 31:0 – RW 0x00

The middle 32 bits of the random seed.

Occupies bits 63:32 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register).

0x38 rand_seed2 31:0 – RW 0x00

The upper 32 bits of the random seed.

Occupies bits 91:64 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register).

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