AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

1.1.1.1. Ethernet Packet Generator

Figure 4. Ethernet Packet Generator Block DiagramThis figure shows a high-level block diagram of the Ethernet Packet Generator module.
Table 2.  Components of the Ethernet Packet Generator
Component Description
Ethernet Packet Generation Block
  • The Ethernet packet generation block generates an Ethernet packet header, data payload and running sequence number for each packet.
  • The Ethernet packet generation block sends the packets to the CRC Generator and the RAM-based Shift Register IP core.
CRC Generator
  • The CRC Generator calculates the CRC-32 checksum for the packet and the RAM-based shift register megafunction stores the packet until the checksum is available.
  • After the generator merges the valid CRC-32 checksum with the packet stream, it sends the complete packet to the Avalon-ST source interface.
Avalon-MM Registers
  • The Avalon-MM slave interface provides access to the Avalon-MM register interface. Using a Tcl script, you can configure the Avalon-MM configuration registers.
  • The Avalon-MM status registers provide the status of the transmit operation and report the number of packets that were successfully transmitted.

    Refer to Ethernet Packet Generator Configuration Registers for more information.

Shift Register (RAM-based) IP Core The Shift Register IP core implements a shift register with taps.

Refer to the RAM-Based Shift Register IP Core User Guide for more information.

Figure 5. Ethernet Packet Generator Output Frame FormatThe figure shows the format the Avalon-ST source interface streams Ethernet packets. The generated packets do not include the 7-byte preamble, 1-byte start frame delimiter (SFD) and 4-byte MAC-calculated Frame Check Sequence (FCS) fields.
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