AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

2. Document Revision History

Date Version Changes
December 2015 2015.12.14
  • Added information about Arria 10 reference design.
  • Removed information about the obsoleted Arria II GX reference design.
December 2012 2012.12.03 Added device support and restructured reference design topic.
Sept 2011 2011.09.23 Updated the link to the design example download page.
June 2011 2011.06.17 Initial release.
Level Two Title