AN 647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design

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ID 683344
Date 12/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design 2. Document Revision History
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design x
1.1. System Architecture 1.2. Interface Signals 1.3. Base Addresses and Configuration Registers 1.4. Running the Reference Designs
1.1. System Architecture x
1.1.1. Design Components
1.1.1. Design Components x
1.1.1.1. Ethernet Packet Generator 1.1.1.2. Ethernet Packet Monitor
1.3. Base Addresses and Configuration Registers x
1.3.1. Ethernet Packet Generator Configuration Registers 1.3.2. Ethernet Packet Monitor Configuration Registers
1.4. Running the Reference Designs x
1.4.1. Hardware and Software Requirements 1.4.2. Internal MAC Loopback Test 1.4.3. Avalon-ST Reverse Loopback Test 1.4.4. Tcl Script
1.4.4. Tcl Script x
1.4.4.1. Configuration Script 1.4.4.2. Ethernet Packet Generator Script
1.4.4.2. Ethernet Packet Generator Script x
1.4.4.2.1. JTAG Connection Port for Altera Devices
1. Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
2. Document Revision History

1.1.1.2. Ethernet Packet Monitor

Figure 6. Ethernet Packet Monitor Block DiagramThis figure shows a high-level block diagram of the Ethernet Packet Monitor module.
Table 3.  Components of the Ethernet Packet Monitor
Component Description
CRC Checker
  • The Avalon-ST sink interface accepts Ethernet packets and sends the packets to the CRC Checker.
  • The CRC Checker computes the CRC-32 checksum of the receive packet and verifies it against the CRC-32 checksum field in the packet.
  • The checker then outputs a status signal that identifies whether the packet received is good or corrupted, and updates the statistics counters accordingly.
Avalon-MM Registers
  • The Avalon-MM slave interface provides access to the Avalon-MM register interface.
  • Using a Tcl script, you can configure the Avalon-MM configuration registers to specify the number of packets the monitor expects to receive.
  • The Avalon-MM status registers provide the status of the receive operation and report the number of good and bad packets received, the number of bytes received, and the number of clock cycles. This information is used to calculate the performance and throughput rate of the reference designs.

    Refer to Ethernet Packet Monitor Configuration Registers for more information.

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