Intel® High Level Synthesis Compiler Standard Edition: User Guide

ID 683306
Date 12/18/2019
Document Table of Contents

A.3. Reviewing Loop Information

The Throughput Analysis section of the high-level design reports (<result>.prj/reports/report.html) file contains information about all the loops in your design and their unroll statuses. This loop analysis report helps you examine whether the Intel® HLS Compiler Standard Edition is able to maximize the throughput of your component.

You can use the loop analysis report to help determine where to deploy one or more of the following pragmas on your loops:
  1. Click Throughput Analysis > Loop Analysis.
  2. In the analysis pane, select Show fully unrolled loops to obtain information about the loops in your design.