Intel® High Level Synthesis Compiler Standard Edition: User Guide

ID 683306
Date 12/18/2019
Document Table of Contents

A.7. Accessing HLD FPGA Reports in JSON Format

The High-Level Design Report data for the Intel® HLS Compiler Standard Edition is also available as JSON-formatted data.

The JSON files containing the report data are available in the <result>.prj /reports/lib/json directory. The directory provides the following .json files:

Table 6.  JSON Files in the <result>.prj/reports/lib/json Directory
File Description
area.json Area Analysis of System
area_src.json Area Analysis of Source
info.json Summary
loops.json Loop Analysis
mav.json Component Viewer
lmv.json Component Memory Viewer
quartus.json Summary
summary.json Summary
warnings.json Summary

You can read the following .json files without a special parser:

  • area.json
  • area_src.json
  • loops.json
  • quartus.json
  • summary.json

For example, if you want to identify all of the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the children section in the loops.json file, as shown below:

“name”:”<block name|Component: component name>  # Find the loops which does not begin with “Component:”
      “data”:[<Yes|No>, <#|n/a>, <II|n/a>]      # The data field corresponds to “Pipelined”, “II”, “Bottleneck”

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