1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
8. Integrating your IP into a System
To integrate your HLS compiler-generated IP into a system with Intel® Quartus® Prime, you must be familiar with Intel® Quartus® Prime Standard Edition as well as the Platform Designer (formerly Qsys) system integration tool included with Intel® Quartus® Prime.
The <result>.prj/components directory contains all the files you need to include your IP in an Intel® Quartus® Prime project.The IP that the HLS compiler generates for each component is self contained. You can move the folders in the components directory to a different location or machine if desired.
Important prerequsite for Intel® Max® 10 FPGA users:
If you develop your component IP for Intel® MAX® 10 devices and you want to integrate your component IP into a system that you are developing in Intel® Quartus® Prime, ensure that the Intel® Quartus® Prime settings file (.qsf) for your system contains one of the following lines:
- set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
- set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM"
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