Intel® High Level Synthesis Compiler Standard Edition: User Guide

ID 683306
Date 12/18/2019
Document Table of Contents

2.1. High Level Synthesis Design Flow

The Intel® High Level Synthesis (HLS) Compiler helps speed your IP development by letting you compile your IP component C++ code to different targets, depending on where you are in your IP development cycle.
The typical design flow when you use the Intel® HLS Compiler Standard Edition consists of the following stages:
  1. Creating your component and testbench.

    You can write a complete C++ application that contains both your component code and your testbench code.

    For details, see Creating a High-Level Synthesis Component and Testbench.

  2. Verify the functionality of your component algorithm and testbench.

    Verify the functionality by compiling your design to an x86-64 executable and running the executable. For details, see Verifying the Functionality of Your Design.

  3. Optimize and refine the FPGA performance of your component.

    Optimize the FPGA performance of your component by compiling your design for an FPGA target device and reviewing the High-Level Design Reports to see where you can optimize your component. This step generates RTL code for your component. For details, see Optimizing and Refining Your Component.

    After initial optimizations, you can see where to further refine your component by simulating your component. For details, see Simulating Your Design.

  4. Synthesize your component with Intel® Quartus® Prime software.

    For details, see Synthesize your Component with Intel Quartus Prime Standard Edition.

    Synthesizing your component generates accurate quality-of-results (QoR) metrics like FPGA area utilization and fMAX.

  5. Integrate your IP into a system with Intel® Quartus® Prime or Platform Designer (formerly Qsys).

    For details, see Integrating your IP into a System.

The following flowchart shows a coarse-grained progression through the stages of a typical Intel® High Level Synthesis (HLS) Compiler design flow.
Figure 1. Overview of Procedure for Synthesizing IP for Intel® FPGA Products