Intel® High Level Synthesis Compiler Standard Edition: User Guide

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ID 683306
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
6. Simulating Your Design x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Standard Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High Level Design Reports (report.html) x
A.1. High Level Design Report Layout A.2. Reviewing the Report Summary A.3. Reviewing Loop Information A.4. Reviewing Component Area Usage A.5. Viewing Component Design A.6. Reviewing Your Component Verification Results A.7. Accessing HLD FPGA Reports in JSON Format
A.3. Reviewing Loop Information x
A.3.1. Loop Analysis Example
A.4. Reviewing Component Area Usage x
A.4.1. Area Analysis Example
A.5. Viewing Component Design x
A.5.1. Reviewing Component Interfaces A.5.2. Reviewing Memory Replication and Stallable LSU Information A.5.3. Viewing Your Component Memory System
1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide

2.1. High Level Synthesis Design Flow

The Intel® High Level Synthesis (HLS) Compiler helps speed your IP development by letting you compile your IP component C++ code to different targets, depending on where you are in your IP development cycle.
The typical design flow when you use the Intel® HLS Compiler Standard Edition consists of the following stages:
  1. Creating your component and testbench.

    You can write a complete C++ application that contains both your component code and your testbench code.

    For details, see Creating a High-Level Synthesis Component and Testbench.

  2. Verify the functionality of your component algorithm and testbench.

    Verify the functionality by compiling your design to an x86-64 executable and running the executable. For details, see Verifying the Functionality of Your Design.

  3. Optimize and refine the FPGA performance of your component.

    Optimize the FPGA performance of your component by compiling your design for an FPGA target device and reviewing the High-Level Design Reports to see where you can optimize your component. This step generates RTL code for your component. For details, see Optimizing and Refining Your Component.

    After initial optimizations, you can see where to further refine your component by simulating your component. For details, see Simulating Your Design.

  4. Synthesize your component with Intel® Quartus® Prime software.

    For details, see Synthesize your Component with Intel Quartus Prime Standard Edition.

    Synthesizing your component generates accurate quality-of-results (QoR) metrics like FPGA area utilization and fMAX.

  5. Integrate your IP into a system with Intel® Quartus® Prime or Platform Designer (formerly Qsys).

    For details, see Integrating your IP into a System.

The following flowchart shows a coarse-grained progression through the stages of a typical Intel® High Level Synthesis (HLS) Compiler design flow.
Figure 1. Overview of Procedure for Synthesizing IP for Intel® FPGA Products
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