ID 683306
Date 12/18/2019
Public

## 5. Optimizing and Refining Your Component

After you have verified the functionality of your component and testbench, you can compile your component to RTL and review the high-level design report to further optimize and refine your component design. The high-level design report shows estimates of various aspects of how your component will be implemented in hardware.
By compiling your component to RTL and reviewing the high-level design report, you can see how your code changes affect your component hardware implementation without needing to run a simulation or a synthesizing hardware through a full Quartus compilation.
To compile your component to RTL without running a simulation, issue the following command:
i++ -march="<FPGA_family_or_part_number>" --simulator none
You can also compile your component with a ModelSim* simulation testbench by omitting the --simulator none option. Compiling without a simulation test bench is faster, but you cannot measure component latency or create waveforms without simulation.

### The Intel® HLS Compiler High-Level Design Reports (report.html)

The High-Level Design Reports are a collection of reports accessed through an HTML file called report.html that you can view in a web browser. You can find the high-level design report in the <name>.prj/reports folder created when you compile your component to RTL.

Use the high-level design report to review information about your component, including the following information:
• Loop information, including unroll status, pipelining status, and initiation interval
• Component visualization including load-store units, component interfaces, loops, and local memory systems

After you simulate your component, the verification statistics report is populated with information such as component latency and the occupancy of I/O interfaces. For more details about your simulation, generate and view ModelSim* waveforms.

After you synthesize your component with Intel® Quartus® Prime software, the following additional information is available in the report:
• Maximum clock frequency (fMAX)
• Accurate area usage estimate

For more information about the high-level design report and how to use it to optimize and refine your component, see Reviewing the High Level Design Reports (report.html).

For information about techniques that you can apply to optimize and refine your component, see Intel® High Level Synthesis Compiler Standard Edition Best Practices Guide.