DisplayPort IP User Guide

ID 683273
Date 7/15/2025
Public
Document Table of Contents

13.1. GTS DisplayPort PHY IP Parameters ( Agilex™ 5 Designs Only)

For Agilex™ 5 designs only, the GTS DisplayPort PHY IP provides the following configurable parameters on three tabs in the parameter editor. Depending on the Phy configuration that you specify in the initial IP tab, the RX and TX tabs appear or disappear.
Figure 57. GTS DisplayPort PHY IP


Table 253.   DisplayPort IP IP parameters
Parameter Supported Values Default Setting Description
PHY Configuration
  • RX
  • TX
  • Duplex
Duplex Selects the PHY configuration as either RX, TX, or Duplex. Agilex™ 5 introduces a fully duplex PHY option, enabling you to simplify your design by avoiding the complexity of Dual Simplex flow and eliminating the DS tool requirement.
Note: In a DS flow, you create two simplex PHYs (RX and TX) and merge them using the DS tool.
Common Lanes
  • 1
  • 2
  • 4
4 The DisplayPort Protocol is built to support 1, 2, or 4 lanes, matching the altera_dp configuration. This configuration allocates either 1, 2, or 4 transceiver channels and adjusts the interface width between the phy and protocol core.
Important: : Ensure the PHY and protocol core settings match, as mismatches cause malfunctions. Currently, there is no way to detect this issue in your design.
Transceiver Clocking
  • PMA Direct
  • System PLL
PMA Direct The DisplayPort PHY in Agilex™ 5 requires a fixed 150MHz reference clock for the transceiver to support all line rates for both RX and TX from 150MHz.

Agilex™ 5 has more flexible GTS-Quads than the F-Tile, making it more suitable for a flexible clocking architecture. To bypass Agilex™ 7 restrictions, the GUI allows you to choose between PMA or system clocking flows. If you select system clocking, the PLL defaults to the common Video Connectivity rate of 700MHz, but you have the option to override this frequency for custom applications.

When you implement system PLL clocking, the DPHY's resource count increases due to the need for extra DC FIFOs. You instantiate the system PLL, which is a design IP, outside of the PHY, following the same process used in Agilex™ 7. For more details, please refer to the Clocking Section.
Enable Transceiver Toolkit
  • On
  • Off
Off When turned on, enables you to tune your TX parameters and measure RX performance. Due to GTS DisplayPort restrictions, you cannot modify any RX parameters within the GTS, as they automatically adapt. Attempts to change RX parameters do not affect the final design and typically lead to an RBC violation, which causes the fitter to fail. You can modify only the four Analog parameters in Transmitter tab. After you have selected your settings, enter them into the Transmitter GUI tab. Refer to Table 254
Refclock Monitoring
  • Disabled
  • Enable Recovery Function
Disabled The GTS IP disables the refclock pin if any interruption or discontinuity in the signal occurs. Each shoreline of the FPGA should have a refclock-monitor to re-enable clocks that might have been inadvertently disabled. Enable this feature in only one GTS instance per shoreline if you require the refclk to be auto-restarted. If the system designer expects no clock interruptions after the FPGA is programmed, then this feature can be left disabled.
Receiver (RX) and Transmitter (TX) Tab
Note: The PHY configuration settings you select in the initial IP tab control the appearance of the RX and TX tabs.
Maximum Line rate
  • RBR 1.62 Gbps
  • HBR1 2.7 Gbps
  • HBR2 5.4 Gbps
  • HBR3 8.1 Gbps
  • UHBR10 10Gbps
  • UHBR13 13.5Gpbs
  • UHBR10 10Gbps
The altera-dp core includes a maximum line rate selector that requires adjustment to align with the specified value. Once you set this value, the width of the interface signals passing between the PHY and the protocol core changes. If the settings between the PHY and the protocol core do not match, the solution does not function correctly. Currently, no method exists to detect this mismatch in the design.