DisplayPort IP User Guide

ID 683273
Date 7/15/2025
Public
Document Table of Contents

11.12.2.9. CONTROL (0x64)

Table 250.  CONTROL (0x64)
Name Bit(s) Access Description Reset
Reserved 31:1
Go 0 RW Setting this bit to 1 causes the CV2AXI core to start data output on the next video frame boundary. 0x0