AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

ID 683265
Date 1/27/2016
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1.3.1.3. Preloader

The Preloader duration is influenced by the following elements:

  • Location of next boot stage
  • Size of next boot stage image
  • Speed of SDRAM (since Preloader loads the image from Flash to SDRAM)
  • Speed of Flash
  • Various Preloader options:
    • SDRAM scrubbing
    • Hardware diagnostic
    • Checking the CRC of the next boot stage image
    • Serial logging
    • Program FPGA

In order to reduce the Preloader duration, the above parameters may be tweaked. For example:

  • Reduce the size of the next boot stage (for example remove networking support from U-Boot if not needed)
  • Use a faster flash (it requires changing Preloader source code – option is not available in Preloader Generator)
  • Disable hardware diagnostic if enabled (uncheck HARDWARE_DIAGNOSTIC in Preloader Generator)
  • Disable serial console output - (uncheck SERIAL_SUPPORT in Preloader Generator)
  • Disable CRC of the next boot stage image (uncheck CHECKSUM_NEXT_IMAGE in Preloader Generator)

If the FPGA programming is selected in the Preloader, then the following also impacts the duration:

  • Location of FPGA Image (QSPI or SD Card FAT partition)
  • Size of the FPGA Image (compression may reduce it significantly)