AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

ID 683265
Date 1/27/2016
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1.2.3. Boot Clocks

The board on which the Cyclone V resides can have different clocking needs:

  • OSC1 input clock can have different values
  • Flash memories can have different clocking requirements
  • Board layout may also impact the maximum flash speeds

In order to accommodate the above, the Boot ROM can be instructed to use different clocking options, through the CSEL pins. The following table presents the CSEL options available on Cyclone V, together with the actual jumper settings on the Cyclone V Development Kit, rev D:

Table 1.  CSEL Options Available
CSEL Cyclone V Dev Kit Switches
J26:CSEL0 J26:CSEL1
0 Right Right
1 Left Right
2 Right Left
3 Left Left
Note: In the following cases the Boot ROM does not touch the clocking at all:
  • CSEL = 0
  • Boot from FPGA
  • Fallback boot from FPGA
  • RAM boot on Warm reset