AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit

ID 683265
Date 1/27/2016
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1.3.1.2. Boot ROM

The duration of the Boot ROM is influenced by the following factors:

  • OSC1 Clock Frequency (for the portion before setting the PLLs or when using CSEL=00)
  • Clocking option (selected by CSEL pins)
  • Boot Source (SD/MMC, QSPI, NAND or FPGA – selected by BSEL pins)
  • Performance of external flash device
  • Size of Preloader image

The above parameters can be tweaked in order to optimize the Boot ROM duration. For example, the OSC1 and CSEL should be selected such that the maximum possible clock values are used for both the MPU and the external flash.

Another example - Tweaking the Preloader so that it is made smaller. The smaller the Preloader, the less time the Boot ROM spends loading it from flash.

For the boot from FPGA option, the Preloader loading time is reduced to zero. But the FPGA has to be already configured for this to be possible, and this takes time, as well.