Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Document Table of Contents

2.3.4. Returning Incorrect Function Number


While using the Intel FPGA P-Tile Hard IP for PCIe, the last Physical Function (PF) indicates incorrect next function number if the following conditions are true:
  • Alternative Routing-ID Interpretation (ARI) capability is enabled
  • Number of Physical Functions (PFs) is less than 8
The next function number incorrectly shows a value of PF+1. As a result, the correctable error status register in the Advanced Error Reporting (AER) capability structure of the root port may report a non-fatal error.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in Endpoint mode
  • Intel FPGA P-Tile Avalon® Memory-Mapped Interface IP for PCIe in Endpoint mode


To avoid this issue, the user logic must use the Configuration Intercept Interface (CII) to override the read data for the next function number when the above conditions are true.

The user logic must clear the correctable error status register of the AER capability using the Hard IP Reconfiguration interface.


  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.