Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Public
Document Table of Contents

2.3.2. TLP Bypass Error Status Register may Report Receiver Errors

Description

During the TLP Bypass implementation using the Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe, the tlpbypass_err_status register of port configuration and status registers (address: 0x104190[8]) may report receiver errors after the PERST is released. Therefore, if the user logic implements the Advanced Error Reporting (AER) capability based on the tlpbypass_err_status register, the correctable error status register of the AER capability indicates receiver errors.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in TLP Bypass mode

Workaround

While using the Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe, the user logic must clear the tlpbypass_err_status register’s receiver error status bit (0x104190[8]) of the port configuration and status registers before the PERST is released.

Status

Affects:
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.