Intel® Stratix® 10 DX Device Errata

ID 683249
Date 11/01/2022
Public
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2.3.6. Register Implementation while using the SR-IOV Feature

Description

While using the Intel FPGA P-Tile Hard IP for PCIe:
  • When the SR-IOV feature is enabled:
    • The PCIe capability link status register (offset 0x082h bits [15:0]) returns the parent PF link status register values when accessed by virtual functions. According to the PCIe Base specification revision 4.0 version 1.0, when SR-IOV feature is enabled, this register must be implemented as Reserved and Zero (RsvdZ) and accessed by virtual functions.
    • The PCIe device control2 register (offset 0x098h bit [12]: 10-bit tag requested enable bit) returns the parent PF device control2 register values when accessed by virtual functions. According to the PCIe Base specification revision 4.0 version 1.0, when SR-IOV feature is enabled, this register must be implemented as Reserved and Preserved (RsvdP) and accessed by virtual functions.
    • The PCIe Address Translation Service (ATS) control register (ATS base address + offset 0x006h bit [4:0]: smallest translation unit (STU) bits) is implemented as read-only (RO) register but returns the value of the parent PF when accessed by virtual functions. According to the PCIe Base specification revision 4.0 version 1.0, this register must be implemented as a read-only (RO) register and hard-wired to 0 when accessed by virtual functions.
These issues do not cause functional failure.

Impacted Modes

  • Intel FPGA P-Tile Avalon® Streaming Interface Hard IP for PCIe in Endpoint mode
  • Intel FPGA P-Tile Avalon® Memory-Mapped Interface IP for PCIe in Endpoint mode

Workaround

The application logic can use Configuration Intercept Interface (CII) or Direct User Avalon Memory-Mapped Interface to modify the configuration accesses to this register.

Status

Affects:
  • Intel® Stratix® 10 DX 2800
  • Intel® Stratix® 10 DX 2100
  • Intel® Stratix® 10 DX 1100

Status: No planned fix.